Module prim_generic_clock_gating

prim_generic_clock_gating #( .NoFpgaGate(NoFpgaGate), .FpgaBufGlobal(FpgaBufGlobal) ) u_prim_generic_clock_gating ( .clk_i(clk_i), .en_i(en_i), .test_en_i(test_en_i), .clk_o(clk_o) );

Block Diagram of prim_generic_clock_gating

Common Library

Clock Gating cell

The logic assumes that en_i is synchronized (so the instantiation site might need to put a synchronizer before en_i).

Parameters

Name	Default	Description
NoFpgaGate	1'b0	this parameter has no function in generic
FpgaBufGlobal	1'b1	this parameter has no function in generic

Ports

Name	Type	Direction	Description
clk_i	wire logic	input
en_i	wire logic	input
test_en_i	wire logic	input
clk_o	var logic	output

Instances

• ibex_top : ibex_top

  • core_clock_gate_i : prim_clock_gating

    • gen_generic : []

      • u_impl_generic : prim_generic_clock_gating

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