[source]

Module ibex_load_store_unit

MemECCMemDataWidthclk_ilogicrst_nilogicdata_gnt_ilogicdata_rvalid_ilogicdata_bus_err_ilogicdata_pmp_err_ilogicdata_rdata_i[MemDataWidth-1:0]logiclsu_we_ilogiclsu_type_i[1:0]logiclsu_wdata_i[31:0]logiclsu_sign_ext_ilogiclsu_req_ilogicadder_result_ex_i[31:0]logicdata_req_ologicdata_addr_ologic[31:0]data_we_ologicdata_be_ologic[3:0]data_wdata_ologic[MemDataWidth-1:0]lsu_rdata_ologic[31:0]lsu_rdata_valid_ologicaddr_incr_req_ologicaddr_last_ologic[31:0]lsu_req_done_ologiclsu_resp_valid_ologicload_err_ologicload_resp_intg_err_ologicstore_err_ologicstore_resp_intg_err_ologicbusy_ologicperf_load_ologicperf_store_ologic

Block Diagram of ibex_load_store_unit

Parameters

Name

Default

Description
MemECC

1'b0
MemDataWidth

MemECC?32+7:32
Ports

Name

Type

Direction

Description
clk_i

wire logic

input
rst_ni

wire logic

input
data_req_o

var logic

output

data interface
data_gnt_i

wire logic

input
data_rvalid_i

wire logic

input
data_bus_err_i

wire logic

input
data_pmp_err_i

wire logic

input
data_addr_o

var logic [31 : 0]

output
data_we_o

var logic

output
data_be_o

var logic [3 : 0]

output
data_wdata_o

var logic [MemDataWidth - 1 : 0]

output
data_rdata_i

wire logic [MemDataWidth - 1 : 0]

input
lsu_we_i

wire logic

input

signals to/from ID/EX stage write enable -> from ID/EX
lsu_type_i

wire logic [1 : 0]

input

data type

word, half word, byte -> from ID/EX

lsu_wdata_i

wire logic [31 : 0]

input

data to write to memory -> from ID/EX
lsu_sign_ext_i

wire logic

input

sign extension -> from ID/EX
lsu_rdata_o

var logic [31 : 0]

output

requested data -> to ID/EX
lsu_rdata_valid_o

var logic

output
lsu_req_i

wire logic

input

data request -> from ID/EX
adder_result_ex_i

wire logic [31 : 0]

input

address computed in ALU -> from ID/EX
addr_incr_req_o

var logic

output

request address increment for
addr_last_o

var logic [31 : 0]

output

misaligned accesses -> to ID/EX address of last transaction -> to controller
lsu_req_done_o

var logic

output

-> mtval -> AGU for misaligned accesses Signals that data request is complete
lsu_resp_valid_o

var logic

output

(only need to await final data response) -> to ID/EX LSU has response from transaction -> to ID/EX
load_err_o

var logic

output

exception signals
load_resp_intg_err_o

var logic

output
store_err_o

var logic

output
store_resp_intg_err_o

var logic

output
busy_o

var logic

output
perf_load_o

var logic

output
perf_store_o

var logic

output
Assertions

Name

Kind

Description

ibex_load_store_unit.IbexDataTypeKnown

concurent assert

Selectors must be known/valid.

disable iff((!rst_ni)!=='0)((lsu_req_i | busy_o) |-> ! $isunknown(lsu_type_i))

ibex_load_store_unit.IbexDataOffsetKnown

concurent assert

 
disable iff((!rst_ni)!=='0)((lsu_req_i | busy_o) |-> ! $isunknown(data_offset))

ibex_load_store_unit.IbexRDataOffsetQKnown

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(rdata_offset_q)

ibex_load_store_unit.IbexDataTypeQKnown

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(data_type_q)

ibex_load_store_unit.IbexLsuStateValid

concurent assert

 
disable iff((!rst_ni)!=='0)(ls_fsm_cs inside {IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, WAIT_RVALID_MIS_GNTS_DONE})

ibex_load_store_unit.IbexDataAddrUnknown

concurent assert

Address must not contain X when request is sent.

disable iff((!rst_ni)!=='0)(data_req_o |-> ! $isunknown(data_addr_o))

ibex_load_store_unit.IbexDataAddrUnaligned

concurent assert

Address must be word aligned when request is sent.

disable iff((!rst_ni)!=='0)(data_req_o |-> (data_addr_o[1 : 0] == 2'b00))

Always Blocks

always_comb @()

///////////////// BE generation // /////////////////

always_comb @()

prepare data to be written to the memory we handle misaligned accesses, half word and byte accesses here

always_ff @(posedge clk_i or negedge rst_ni)

register for unaligned rdata

always_ff @(posedge clk_i or negedge rst_ni)

registers for transaction control

always_comb @()

take care of misaligned words

always_comb @()

sign extension for half words

always_comb @()

sign extension for bytes

always_comb @()

select word, half word or byte sign extended version

always_comb @()

FSM

always_ff @(posedge clk_i or negedge rst_ni)

registers for FSM

IDLE IDLE WAIT_GNT_MIS WAIT_GNT_MIS WAIT_RVALID_MIS WAIT_RVALID_MIS WAIT_GNT WAIT_GNT WAIT_RVALID_MIS_GNTS_DONE WAIT_RVALID_MIS_GNTS_DONE 2 [((lsu_req_i) && !(data_gnt_i) && (split_misaligned_access))] 1 [((lsu_req_i) && (data_gnt_i) && (split_misaligned_access))] 3 [(!(split_misaligned_access) && (lsu_req_i) && !(data_gnt_i))] 7 [(data_gnt_i || pmp_err_q)] 4 [(!(data_gnt_i) && (data_rvalid_i || pmp_err_q))] 6 [(!(data_rvalid_i || pmp_err_q) && (data_gnt_i))] 5 [((data_rvalid_i || pmp_err_q) && (data_gnt_i))] 8 [(data_gnt_i || pmp_err_q)] 9 [(data_rvalid_i)]
FSM Transitions for ls_fsm_cs

#

Current State

Next State

Condition

Comment

1

IDLE

WAIT_RVALID_MIS

[((lsu_req_i) && (data_gnt_i) && (split_misaligned_access))]

2

IDLE

WAIT_GNT_MIS

[((lsu_req_i) && !(data_gnt_i) && (split_misaligned_access))]

3

IDLE

WAIT_GNT

[(!(split_misaligned_access) && (lsu_req_i) && !(data_gnt_i))]

4

WAIT_RVALID_MIS

WAIT_GNT

[(!(data_gnt_i) && (data_rvalid_i || pmp_err_q))]

5

WAIT_RVALID_MIS

IDLE

[((data_rvalid_i || pmp_err_q) && (data_gnt_i))]

6

WAIT_RVALID_MIS

WAIT_RVALID_MIS_GNTS_DONE

[(!(data_rvalid_i || pmp_err_q) && (data_gnt_i))]

7

WAIT_GNT_MIS

WAIT_RVALID_MIS

[(data_gnt_i || pmp_err_q)]

8

WAIT_GNT

IDLE

[(data_gnt_i || pmp_err_q)]

9

WAIT_RVALID_MIS_GNTS_DONE

IDLE

[(data_rvalid_i)]

Instances

Submodules

  • ibex_load_store_unit

    • g_no_mem_data_ecc : [if !(MemECC)]

    • g_no_mem_wdata_ecc : [if !(MemECC)]

load_store_unit_i (ibex_load_store_unit)

Flow Diagram of ibex_load_store_unit

g_no_mem_data_ecc g_no_mem_wdata_ecc load_store_unit_i (ibex_load_store_unit)

Sub-Instances Diagram of ibex_load_store_unit

data_addr adder_result_ex_i data_offset data_addr addr_last_d data_addr_w_aligned addr_incr_req_o data_addr split_misaligned_access lsu_type_i data_offset lsu_req_done_o lsu_req_i ls_fsm_cs ls_fsm_ns data_or_pmp_err lsu_err_q data_bus_err_i pmp_err_q lsu_resp_valid_o data_rvalid_i pmp_err_q ls_fsm_cs lsu_rdata_valid_o ls_fsm_cs data_rvalid_i data_or_pmp_err data_we_q data_intg_err lsu_rdata_o data_rdata_ext data_addr_w_aligned data_addr data_addr_o data_addr_w_aligned data_we_o lsu_we_i data_be_o data_be addr_last_o addr_last_q load_err_o data_or_pmp_err data_we_q lsu_resp_valid_o store_err_o data_or_pmp_err data_we_q lsu_resp_valid_o load_resp_intg_err_o data_intg_err data_rvalid_i data_we_q store_resp_intg_err_o data_intg_err data_rvalid_i data_we_q busy_o ls_fsm_cs fcov_mis_rvalid_1 ls_fsm_cs data_rvalid_i fcov_mis_rvalid_2 ls_fsm_cs fcov_mis_2_en_q data_rvalid_i fcov_mis_2_en_d fcov_mis_rvalid_2 fcov_mis_rvalid_1 fcov_mis_2_en_q fcov_mis_bus_err_1_d fcov_mis_rvalid_2 fcov_mis_rvalid_1 data_bus_err_i fcov_mis_bus_err_1_q fcov_ls_error_exception load_err_o store_err_o pmp_err_q unused_fcov_ls_error_exception fcov_ls_error_exception fcov_ls_pmp_exception load_err_o store_err_o pmp_err_q unused_fcov_ls_pmp_exception fcov_ls_pmp_exception fcov_ls_first_req lsu_req_i ls_fsm_cs unused_fcov_ls_first_req fcov_ls_first_req fcov_ls_second_req ls_fsm_cs data_req_o addr_incr_req_o unused_fcov_ls_second_req fcov_ls_second_req fcov_ls_mis_pmp_err_1 ls_fsm_cs pmp_err_q unused_fcov_ls_mis_pmp_err_1 fcov_ls_mis_pmp_err_1 fcov_ls_mis_pmp_err_2 ls_fsm_cs data_pmp_err_i unused_fcov_ls_mis_pmp_err_2 fcov_ls_mis_pmp_err_2 data_be lsu_type_i handle_misaligned_q data_offset data_wdata lsu_wdata_i data_offset rdata_w_ext data_rdata_i rdata_offset_q rdata_q rdata_h_ext data_rdata_i rdata_offset_q data_sign_ext_q rdata_q rdata_b_ext data_rdata_i rdata_offset_q data_sign_ext_q data_rdata_ext rdata_w_ext data_type_q rdata_h_ext rdata_b_ext ls_fsm_ns ls_fsm_cs data_gnt_i pmp_err_q data_rvalid_i lsu_req_i split_misaligned_access data_req_o addr_incr_req_o handle_misaligned_q handle_misaligned_d pmp_err_d data_pmp_err_i lsu_err_d lsu_err_q data_bus_err_i addr_update ctrl_update rdata_update data_we_q perf_load_o lsu_we_i perf_store_o rdata_q rst_ni clk_i data_rdata_i rdata_update rdata_offset_q rst_ni clk_i data_offset ctrl_update data_type_q lsu_type_i data_sign_ext_q lsu_sign_ext_i data_we_q lsu_we_i addr_last_q rst_ni clk_i addr_last_d addr_update ls_fsm_cs rst_ni clk_i ls_fsm_ns handle_misaligned_q handle_misaligned_d pmp_err_q pmp_err_d lsu_err_q lsu_err_d fcov_mis_2_en_q rst_ni clk_i fcov_mis_2_en_d fcov_mis_bus_err_1_q fcov_mis_bus_err_1_d data_intg_err g_no_mem_data_ecc data_wdata_o data_wdata g_no_mem_wdata_ecc load_store_unit_i (ibex_load_store_unit) clk_i rst_ni data_req_o data_gnt_i data_rvalid_i data_bus_err_i data_pmp_err_i data_addr_o data_we_o data_be_o data_wdata_o data_rdata_i lsu_we_i lsu_type_i lsu_wdata_i lsu_sign_ext_i lsu_rdata_o lsu_rdata_valid_o lsu_req_i adder_result_ex_i addr_incr_req_o addr_last_o lsu_req_done_o lsu_resp_valid_o load_err_o load_resp_intg_err_o store_err_o store_resp_intg_err_o busy_o perf_load_o perf_store_o

Schematic Diagram of ibex_load_store_unit