[source]

Module prim_generic_flop

WidthResetValueclk_ilogicrst_nilogicd_i[Width-1:0]logicq_ologic[Width-1:0]

Block Diagram of prim_generic_flop

Parameters

Name

Default

Description

Width

1

ResetValue

0

Ports

Name

Type

Direction

Description

clk_i

wire logic

input

rst_ni

wire logic

input

d_i

wire logic [Width - 1 : 0]

input

q_o

var logic [Width - 1 : 0]

output