[source]

Module prim_secded_22_16_enc

data_i[15:0]logicdata_ologic[21:0]

Block Diagram of prim_secded_22_16_enc

SECDED encoder generated by util/design/secded_gen.py

Ports

Name

Type

Direction

Description

data_i

wire logic [15 : 0]

input

data_o

var logic [21 : 0]

output