Module prim_secded_22_16_dec
Block Diagram of prim_secded_22_16_dec
Name |
Type |
Direction |
Description |
---|---|---|---|
data_i |
wire logic [21 : 0] |
input |
|
data_o |
var logic [15 : 0] |
output |
|
syndrome_o |
var logic [5 : 0] |
output |
|
err_o |
var logic [1 : 0] |
output |
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SECDED decoder generated by util/design/secded_gen.py