[source]

Module prim_secded_22_16_dec

data_i[21:0]logicdata_ologic[15:0]syndrome_ologic[5:0]err_ologic[1:0]

Block Diagram of prim_secded_22_16_dec

SECDED decoder generated by util/design/secded_gen.py

Ports

Name

Type

Direction

Description

data_i

wire logic [21 : 0]

input

data_o

var logic [15 : 0]

output

syndrome_o

var logic [5 : 0]

output

err_o

var logic [1 : 0]

output