Module prim_flop
Block Diagram of prim_flop
Name |
Default |
Description |
|---|---|---|
Width |
1 |
|
ResetValue |
0 |
Name |
Type |
Direction |
Description |
|---|---|---|---|
clk_i |
wire logic |
input |
|
rst_ni |
wire logic |
input |
|
d_i |
wire logic [Width - 1 : 0] |
input |
|
q_o |
var logic [Width - 1 : 0] |
output |
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Abstract primitives wrapper.
This file is a stop-gap until the DV file list is generated by FuseSoC. Its contents are taken from the file which would be generated by FuseSoC. https://github.com/lowRISC/ibex/issues/893