Module ibex_multdiv_slow

ibex_multdiv_slow u_ibex_multdiv_slow ( .clk_i(clk_i), .rst_ni(rst_ni), .mult_en_i(mult_en_i), .div_en_i(div_en_i), .mult_sel_i(mult_sel_i), .div_sel_i(div_sel_i), .operator_i(operator_i), .signed_mode_i(signed_mode_i), .op_a_i(op_a_i), .op_b_i(op_b_i), .alu_adder_ext_i(alu_adder_ext_i), .alu_adder_i(alu_adder_i), .equal_to_zero_i(equal_to_zero_i), .data_ind_timing_i(data_ind_timing_i), .alu_operand_a_o(alu_operand_a_o), .alu_operand_b_o(alu_operand_b_o), .imd_val_q_i(imd_val_q_i), .imd_val_d_o(imd_val_d_o), .imd_val_we_o(imd_val_we_o), .multdiv_ready_id_i(multdiv_ready_id_i), .multdiv_result_o(multdiv_result_o), .valid_o(valid_o) );

Block Diagram of ibex_multdiv_slow

Ports

Name	Type	Direction	Description
clk_i	wire logic	input
rst_ni	wire logic	input
mult_en_i	wire logic	input	dynamic enable signal, for FSM control
div_en_i	wire logic	input	dynamic enable signal, for FSM control
mult_sel_i	wire logic	input	static decoder output, for data muxes
div_sel_i	wire logic	input	static decoder output, for data muxes
operator_i	wire ibex_pkg::md_op_e	input
signed_mode_i	wire logic [1 : 0]	input
op_a_i	wire logic [31 : 0]	input
op_b_i	wire logic [31 : 0]	input
alu_adder_ext_i	wire logic [33 : 0]	input
alu_adder_i	wire logic [31 : 0]	input
equal_to_zero_i	wire logic	input
data_ind_timing_i	wire logic	input
alu_operand_a_o	var logic [32 : 0]	output
alu_operand_b_o	var logic [32 : 0]	output
imd_val_q_i	wire logic [33 : 0]	input
imd_val_d_o	var logic [33 : 0]	output
imd_val_we_o	var logic [1 : 0]	output
multdiv_ready_id_i	wire logic	input
multdiv_result_o	var logic [31 : 0]	output
valid_o	var logic	output

Assertions

Name	Kind	Description
ibex_multdiv_slow.IbexMultDivStateValid	concurent assert	State must be valid. disable iff((!rst_ni)!=='0)(md_state_q inside {MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH})

Always Blocks

always_ff @(posedge clk_i or negedge rst_ni)

FSM Transitions for md_state_q

#	Current State	Next State	Condition	Comment
1	MD_IDLE	MD_LAST	[((mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULL) && (! data_ind_timing_i && op_b_ext >> 1 == 0))]
2	MD_IDLE	MD_COMP	[((mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULH)), (!(! data_ind_timing_i && op_b_ext >> 1 == 0) && (mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULL))]
3	MD_IDLE	MD_ABS_A	[(!(! data_ind_timing_i && equal_to_zero_i) && (mult_sel_i || div_sel_i) && (operator_i == MD_OP_DIV)), (!(! data_ind_timing_i && equal_to_zero_i) && (mult_sel_i || div_sel_i) && (operator_i == MD_OP_REM))]
4	MD_IDLE	MD_FINISH	[((mult_sel_i || div_sel_i) && (operator_i == MD_OP_DIV) && (! data_ind_timing_i && equal_to_zero_i)), ((mult_sel_i || div_sel_i) && (operator_i == MD_OP_REM) && (! data_ind_timing_i && equal_to_zero_i))]
5	MD_LAST	MD_IDLE	[((mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULL)), ((mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULH)), ((mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULH))]
6	MD_LAST	MD_CHANGE_SIGN	[((mult_sel_i || div_sel_i) && (operator_i == MD_OP_DIV)), ((mult_sel_i || div_sel_i) && (operator_i == MD_OP_REM))]
7	MD_COMP	MD_LAST	[((mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULL) && (! data_ind_timing_i && op_b_shift_d == 0 || multdiv_count_q == 5'd1)), ((mult_sel_i || div_sel_i) && (operator_i == MD_OP_MULH) && (multdiv_count_q == 5'd1)), ((mult_sel_i || div_sel_i) && (operator_i == MD_OP_DIV, MD_OP_REM) && (multdiv_count_q == 5'd1))]
8	MD_ABS_A	MD_ABS_B	[(mult_sel_i || div_sel_i)]
9	MD_FINISH	MD_IDLE	[(mult_sel_i || div_sel_i)]
10	MD_CHANGE_SIGN	MD_FINISH	[(mult_sel_i || div_sel_i)]
11	MD_ABS_B	MD_COMP	[(mult_sel_i || div_sel_i)]

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