Module ibex_lockstep

ibex_lockstep #( .LockstepOffset(LockstepOffset), .PMPEnable(PMPEnable), .PMPGranularity(PMPGranularity), .PMPNumRegions(PMPNumRegions), .PMPRstCfg(PMPRstCfg), .PMPRstAddr(PMPRstAddr), .PMPRstMsecCfg(PMPRstMsecCfg), .MHPMCounterNum(MHPMCounterNum), .MHPMCounterWidth(MHPMCounterWidth), .RV32E(RV32E), .RV32M(RV32M), .RV32B(RV32B), .BranchTargetALU(BranchTargetALU), .WritebackStage(WritebackStage), .ICache(ICache), .ICacheECC(ICacheECC), .BusSizeECC(BusSizeECC), .TagSizeECC(TagSizeECC), .LineSizeECC(LineSizeECC), .BranchPredictor(BranchPredictor), .DbgTriggerEn(DbgTriggerEn), .DbgHwBreakNum(DbgHwBreakNum), .ResetAll(ResetAll), .RndCnstLfsrSeed(RndCnstLfsrSeed), .RndCnstLfsrPerm(RndCnstLfsrPerm), .SecureIbex(SecureIbex), .DummyInstructions(DummyInstructions), .RegFileECC(RegFileECC), .RegFileDataWidth(RegFileDataWidth), .MemECC(MemECC), .MemDataWidth(MemDataWidth), .DmBaseAddr(DmBaseAddr), .DmAddrMask(DmAddrMask), .DmHaltAddr(DmHaltAddr), .DmExceptionAddr(DmExceptionAddr) ) u_ibex_lockstep ( .clk_i(clk_i), .rst_ni(rst_ni), .hart_id_i(hart_id_i), .boot_addr_i(boot_addr_i), .instr_req_i(instr_req_i), .instr_gnt_i(instr_gnt_i), .instr_rvalid_i(instr_rvalid_i), .instr_addr_i(instr_addr_i), .instr_rdata_i(instr_rdata_i), .instr_err_i(instr_err_i), .data_req_i(data_req_i), .data_gnt_i(data_gnt_i), .data_rvalid_i(data_rvalid_i), .data_we_i(data_we_i), .data_be_i(data_be_i), .data_addr_i(data_addr_i), .data_wdata_i(data_wdata_i), .data_rdata_i(data_rdata_i), .data_err_i(data_err_i), .dummy_instr_id_i(dummy_instr_id_i), .dummy_instr_wb_i(dummy_instr_wb_i), .rf_raddr_a_i(rf_raddr_a_i), .rf_raddr_b_i(rf_raddr_b_i), .rf_waddr_wb_i(rf_waddr_wb_i), .rf_we_wb_i(rf_we_wb_i), .rf_wdata_wb_ecc_i(rf_wdata_wb_ecc_i), .rf_rdata_a_ecc_i(rf_rdata_a_ecc_i), .rf_rdata_b_ecc_i(rf_rdata_b_ecc_i), .ic_tag_req_i(ic_tag_req_i), .ic_tag_write_i(ic_tag_write_i), .ic_tag_addr_i(ic_tag_addr_i), .ic_tag_wdata_i(ic_tag_wdata_i), .ic_tag_rdata_i(ic_tag_rdata_i), .ic_data_req_i(ic_data_req_i), .ic_data_write_i(ic_data_write_i), .ic_data_addr_i(ic_data_addr_i), .ic_data_wdata_i(ic_data_wdata_i), .ic_data_rdata_i(ic_data_rdata_i), .ic_scr_key_valid_i(ic_scr_key_valid_i), .ic_scr_key_req_i(ic_scr_key_req_i), .irq_software_i(irq_software_i), .irq_timer_i(irq_timer_i), .irq_external_i(irq_external_i), .irq_fast_i(irq_fast_i), .irq_nm_i(irq_nm_i), .irq_pending_i(irq_pending_i), .debug_req_i(debug_req_i), .crash_dump_i(crash_dump_i), .double_fault_seen_i(double_fault_seen_i), .fetch_enable_i(fetch_enable_i), .alert_minor_o(alert_minor_o), .alert_major_internal_o(alert_major_internal_o), .alert_major_bus_o(alert_major_bus_o), .core_busy_i(core_busy_i), .test_en_i(test_en_i), .scan_rst_ni(scan_rst_ni) );

Block Diagram of ibex_lockstep

SEC_CM

LOGIC.SHADOW

Parameters

Name	Default	Description
LockstepOffset	2
PMPEnable	1'b0
PMPGranularity	0
PMPNumRegions	4
PMPRstCfg	ibex_pkg::PmpCfgRst
PMPRstAddr	ibex_pkg::PmpAddrRst
PMPRstMsecCfg	ibex_pkg::PmpMseccfgRst
MHPMCounterNum	0
MHPMCounterWidth	40
RV32E	1'b0
RV32M	RV32MFast
RV32B	RV32BNone
BranchTargetALU	1'b0
WritebackStage	1'b0
ICache	1'b0
ICacheECC	1'b0
BusSizeECC	BUS_SIZE
TagSizeECC	IC_TAG_SIZE
LineSizeECC	IC_LINE_SIZE
BranchPredictor	1'b0
DbgTriggerEn	1'b0
DbgHwBreakNum	1
ResetAll	1'b0
RndCnstLfsrSeed	RndCnstLfsrSeedDefault
RndCnstLfsrPerm	RndCnstLfsrPermDefault
SecureIbex	1'b0
DummyInstructions	1'b0
RegFileECC	1'b0
RegFileDataWidth	32
MemECC	1'b0
MemDataWidth	MemECC?32+7:32
DmBaseAddr	32'h1A110000
DmAddrMask	32'h00000FFF
DmHaltAddr	32'h1A110800
DmExceptionAddr	32'h1A110808

Ports

Name	Type	Direction	Description
clk_i	wire logic	input
rst_ni	wire logic	input
hart_id_i	wire logic [31 : 0]	input
boot_addr_i	wire logic [31 : 0]	input
instr_req_i	wire logic	input
instr_gnt_i	wire logic	input
instr_rvalid_i	wire logic	input
instr_addr_i	wire logic [31 : 0]	input
instr_rdata_i	wire logic [MemDataWidth - 1 : 0]	input
instr_err_i	wire logic	input
data_req_i	wire logic	input
data_gnt_i	wire logic	input
data_rvalid_i	wire logic	input
data_we_i	wire logic	input
data_be_i	wire logic [3 : 0]	input
data_addr_i	wire logic [31 : 0]	input
data_wdata_i	wire logic [MemDataWidth - 1 : 0]	input
data_rdata_i	wire logic [MemDataWidth - 1 : 0]	input
data_err_i	wire logic	input
dummy_instr_id_i	wire logic	input
dummy_instr_wb_i	wire logic	input
rf_raddr_a_i	wire logic [4 : 0]	input
rf_raddr_b_i	wire logic [4 : 0]	input
rf_waddr_wb_i	wire logic [4 : 0]	input
rf_we_wb_i	wire logic	input
rf_wdata_wb_ecc_i	wire logic [RegFileDataWidth - 1 : 0]	input
rf_rdata_a_ecc_i	wire logic [RegFileDataWidth - 1 : 0]	input
rf_rdata_b_ecc_i	wire logic [RegFileDataWidth - 1 : 0]	input
ic_tag_req_i	wire logic [IC_NUM_WAYS - 1 : 0]	input
ic_tag_write_i	wire logic	input
ic_tag_addr_i	wire logic [IC_INDEX_W - 1 : 0]	input
ic_tag_wdata_i	wire logic [TagSizeECC - 1 : 0]	input
ic_tag_rdata_i	wire logic [TagSizeECC - 1 : 0]	input
ic_data_req_i	wire logic [IC_NUM_WAYS - 1 : 0]	input
ic_data_write_i	wire logic	input
ic_data_addr_i	wire logic [IC_INDEX_W - 1 : 0]	input
ic_data_wdata_i	wire logic [LineSizeECC - 1 : 0]	input
ic_data_rdata_i	wire logic [LineSizeECC - 1 : 0]	input
ic_scr_key_valid_i	wire logic	input
ic_scr_key_req_i	wire logic	input
irq_software_i	wire logic	input
irq_timer_i	wire logic	input
irq_external_i	wire logic	input
irq_fast_i	wire logic [14 : 0]	input
irq_nm_i	wire logic	input
irq_pending_i	wire logic	input
debug_req_i	wire logic	input
crash_dump_i	wire crash_dump_t	input
double_fault_seen_i	wire logic	input
fetch_enable_i	wire ibex_mubi_t	input
alert_minor_o	var logic	output
alert_major_internal_o	var logic	output
alert_major_bus_o	var logic	output
core_busy_i	wire ibex_mubi_t	input
test_en_i	wire logic	input
scan_rst_ni	wire logic	input

Structs

typedef struct delayed_inputs_t

//////////////// Input delays // ////////////////

typedef struct delayed_outputs_t

///////////////// Output delays // /////////////////

Always Blocks

always_ff @(posedge clk_i or negedge rst_ni)

Delay the inputs

always_ff @(posedge clk_i)

Delay the outputs

always_ff @(posedge clk_i)

Register the shadow core outputs

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