Module ibex_tracer
Block Diagram of ibex_tracer
Name |
Type |
Direction |
Description |
|---|---|---|---|
clk_i |
wire logic |
input |
|
rst_ni |
wire logic |
input |
|
hart_id_i |
wire logic [31 : 0] |
input |
|
rvfi_valid |
wire logic |
input |
RVFI as described at https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md The standard interface does not have _i/_o suffixes. For consistency with the standard the signals in this module don't have the suffixes either. |
rvfi_order |
wire logic [63 : 0] |
input |
|
rvfi_insn |
wire logic [31 : 0] |
input |
|
rvfi_trap |
wire logic |
input |
|
rvfi_halt |
wire logic |
input |
|
rvfi_intr |
wire logic |
input |
|
rvfi_mode |
wire logic [1 : 0] |
input |
|
rvfi_ixl |
wire logic [1 : 0] |
input |
|
rvfi_rs1_addr |
wire logic [4 : 0] |
input |
|
rvfi_rs2_addr |
wire logic [4 : 0] |
input |
|
rvfi_rs3_addr |
wire logic [4 : 0] |
input |
|
rvfi_rs1_rdata |
wire logic [31 : 0] |
input |
|
rvfi_rs2_rdata |
wire logic [31 : 0] |
input |
|
rvfi_rs3_rdata |
wire logic [31 : 0] |
input |
|
rvfi_rd_addr |
wire logic [4 : 0] |
input |
|
rvfi_rd_wdata |
wire logic [31 : 0] |
input |
|
rvfi_pc_rdata |
wire logic [31 : 0] |
input |
|
rvfi_pc_wdata |
wire logic [31 : 0] |
input |
|
rvfi_mem_addr |
wire logic [31 : 0] |
input |
|
rvfi_mem_rmask |
wire logic [3 : 0] |
input |
|
rvfi_mem_wmask |
wire logic [3 : 0] |
input |
|
rvfi_mem_rdata |
wire logic [31 : 0] |
input |
|
rvfi_mem_wdata |
wire logic [31 : 0] |
input |
Always Blocks
- always_ff @(posedge clk_i or negedge rst_ni)
cycle counter
- always @(posedge clk_i)
log execution
Functions
- printbuffer_dumpline(int fh)
- Parameters:
fh (int)
- reg_addr_to_str(logic[4:0] addr)
Format register address with "x" prefix, left-aligned to a fixed width of 3 characters.
- Parameters:
addr (logic[4:0])
- get_csr_name(logic[11:0] csr_addr)
Get a CSR name for a CSR address.
- Parameters:
csr_addr (logic[11:0])
- decode_mnemonic(string mnemonic)
- Parameters:
mnemonic (string)
- decode_r_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_r1_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_r_cmixcmov_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_r_funnelshift_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_i_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_i_shift_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_i_funnelshift_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_i_jalr_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_u_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_j_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_b_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_csr_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_cr_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_ci_cli_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_ci_caddi_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_ci_caddi16sp_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_ci_clui_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_ci_cslli_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_ciw_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_cb_sr_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_cb_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_cs_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_cj_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_compressed_load_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_compressed_store_insn(string mnemonic)
- Parameters:
mnemonic (string)
- decode_load_insn()
- decode_store_insn()
- get_fence_description(logic[3:0] bits)
- Parameters:
bits (logic[3:0])
- decode_fence()
Trace executed instructions in simulation
This tracer takes execution information from the RISC-V Verification Interface (RVFI) and produces a text file with a human-readable trace.
All traced instructions are written to a log file. By default, the log file is named trace_core_.log, with being the 8 digit hart ID of the core being traced.
The file name base, defaulting to "trace_core" can be set using the "ibex_tracer_file_base" plusarg passed to the simulation, e.g. "+ibex_tracer_file_base=ibex_my_trace". The exact syntax of passing plusargs to a simulation depends on the simulator.
The creation of the instruction trace is enabled by default but can be disabled for a simulation. This behaviour is controlled by the plusarg "ibex_tracer_enable". Use "ibex_tracer_enable=0" to disable the tracer.
The trace contains six columns, separated by tabs
The simulation time
The clock cycle count since reset
The program counter (PC)
The instruction
The decoded instruction in the same format as objdump, together with the accessed registers and read/written memory values. Jumps and branches show the target address. This column may be omitted if the instruction does not decode into a long form.
Accessed registers and memory locations.
Significant effort is spent to make the decoding produced by this tracer as similar as possible to the one produced by objdump. This simplifies the correlation between the static program information from the objdump-generated disassembly, and the runtime information from this tracer.