[source]

Module ibex_multdiv_fast

Block Diagram of ibex_multdiv_fast

Parameters
Name	Default	Description
RV32M	ibex_pkg::RV32MFast

Ports
Name	Type	Direction	Description
clk_i	wire logic	input
rst_ni	wire logic	input
mult_en_i	wire logic	input	dynamic enable signal, for FSM control
div_en_i	wire logic	input	dynamic enable signal, for FSM control
mult_sel_i	wire logic	input	static decoder output, for data muxes
div_sel_i	wire logic	input	static decoder output, for data muxes
operator_i	wire ibex_pkg::md_op_e	input
signed_mode_i	wire logic [1 : 0]	input
op_a_i	wire logic [31 : 0]	input
op_b_i	wire logic [31 : 0]	input
alu_adder_ext_i	wire logic [33 : 0]	input
alu_adder_i	wire logic [31 : 0]	input
equal_to_zero_i	wire logic	input
data_ind_timing_i	wire logic	input
alu_operand_a_o	var logic [32 : 0]	output
alu_operand_b_o	var logic [32 : 0]	output
imd_val_q_i	wire logic [33 : 0]	input
imd_val_d_o	var logic [33 : 0]	output
imd_val_we_o	var logic [1 : 0]	output
multdiv_ready_id_i	wire logic	input
multdiv_result_o	var logic [31 : 0]	output
valid_o	var logic	output

Assertions
Name	Kind	Description
ibex_multdiv_fast.DivEnKnown	concurent assert	disable iff((!rst_ni)!=='0)! $isunknown(div_en_internal)
ibex_multdiv_fast.MultEnKnown	concurent assert	disable iff((!rst_ni)!=='0)! $isunknown(mult_en_internal)
ibex_multdiv_fast.MultDivEnKnown	concurent assert	disable iff((!rst_ni)!=='0)! $isunknown(multdiv_en)
ibex_multdiv_fast.IbexMultStateKnown	concurent assert	States must be knwon/valid. disable iff((!rst_ni)!=='0)! $isunknown(mult_state_q)
ibex_multdiv_fast.IbexMultStateKnown	concurent assert	States must be knwon/valid. disable iff((!rst_ni)!=='0)! $isunknown(mult_state_q)
ibex_multdiv_fast.IbexMultDivStateValid	concurent assert	States must be knwon/valid. disable iff((!rst_ni)!=='0)(md_state_q inside {MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH})

Always Blocks

always_comb @()

The adder in the ALU computes alu_operand_a_o + alu_operand_b_o which means

Remainder

Divisor. If Remainder - Divisor >= 0, is_greater_equal is equal to 1,

the next Remainder is Remainder

Divisor contained in res_adder_h and the

FSM Transitions for md_state_q
#	Current State	Next State	Condition
1	MD_IDLE	MD_ABS_A	[(!(! data_ind_timing_i && equal_to_zero_i) && (operator_i == MD_OP_DIV)), (!(! data_ind_timing_i && equal_to_zero_i) && !(operator_i == MD_OP_DIV))]
2	MD_IDLE	MD_FINISH	[((operator_i == MD_OP_DIV) && (! data_ind_timing_i && equal_to_zero_i)), (!(operator_i == MD_OP_DIV) && (! data_ind_timing_i && equal_to_zero_i))]
3	MD_ABS_A	MD_ABS_B	[EMPTY]
4	MD_FINISH	MD_IDLE	[EMPTY]
5	MD_ABS_B	MD_COMP	[EMPTY]
6	MD_COMP	MD_LAST	[(div_counter_q == 5'd1)]
7	MD_LAST	MD_CHANGE_SIGN	[EMPTY]
8	MD_CHANGE_SIGN	MD_FINISH	[EMPTY]