[source]

Module prim_clock_gating

Implclk_ilogicen_ilogictest_en_ilogicclk_ologic

Block Diagram of prim_clock_gating

Parameters

Name

Default

Description

Impl

prim_pkg::ImplGeneric

Ports

Name

Type

Direction

Description

clk_i

wire logic

input

en_i

wire logic

input

test_en_i

wire logic

input

clk_o

var logic

output

Instances

Submodules

gen_generic.u_impl_generic (prim_generic_clock_gating) gen_generic core_clock_gate_i (prim_clock_gating)

Flow Diagram of prim_clock_gating

gen_generic.u_impl_generic (prim_generic_clock_gating) clk_i en_i test_en_i clk_o gen_generic core_clock_gate_i (prim_clock_gating) clk_i en_i test_en_i clk_o

Sub-Instances Diagram of prim_clock_gating

gen_generic.u_impl_generic (prim_generic_clock_gating) clk_i en_i test_en_i clk_o gen_generic core_clock_gate_i (prim_clock_gating) clk_i en_i test_en_i clk_o

Schematic Diagram of prim_clock_gating