Module prim_generic_clock_mux2

prim_generic_clock_mux2 #( .NoFpgaBufG(NoFpgaBufG) ) u_prim_generic_clock_mux2 ( .clk0_i(clk0_i), .clk1_i(clk1_i), .sel_i(sel_i), .clk_o(clk_o) );

Block Diagram of prim_generic_clock_mux2

Parameters

Name	Default	Description
NoFpgaBufG	1'b0	this parameter serves no function in the generic model

Ports

Name	Type	Direction	Description
clk0_i	wire logic	input
clk1_i	wire logic	input
sel_i	wire logic	input
clk_o	var logic	output

Assertions

Name	Kind	Description
prim_generic_clock_mux2.selKnown0	concurent assert	make sure sel is never X (including during reset) need to use ##1 as this could break with inverted clocks that start with a rising edge at the beginning of the simulation. disable iff((0)!=='0)(## 1 ! $isunknown(sel_i))
prim_generic_clock_mux2.selKnown1	concurent assert	disable iff((0)!=='0)(## 1 ! $isunknown(sel_i))

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