Module prim_clock_mux2
Block Diagram of prim_clock_mux2
Name |
Default |
Description |
|---|---|---|
NoFpgaBufG |
1'b0 |
Name |
Type |
Direction |
Description |
|---|---|---|---|
clk0_i |
wire logic |
input |
|
clk1_i |
wire logic |
input |
|
sel_i |
wire logic |
input |
|
clk_o |
var logic |
output |
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Abstract primitives wrapper.
This file is a stop-gap until the DV file list is generated by FuseSoC. Its contents are taken from the file which would be generated by FuseSoC. https://github.com/lowRISC/ibex/issues/893