Copyright 2004-2009 Synopsys, Inc.
Copyright 2010-2011 Mentor Graphics Corporation
Copyright 2010-2011 Cadence Design Systems, Inc.
All Rights Reserved Worldwide
Licensed under the Apache License, Version 2.0 (the
"License"); you may not use this file except in
compliance with the License. You may obtain a copy of
the License at
Unless required by applicable law or agreed to in
writing, software distributed under the License is
distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing
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TITLE
Explicit Register Predictor
The uvm_reg_predictor class defines a predictor component,
which is used to update the register model's mirror values
based on transactions explicitly observed on a physical bus.
Copyright 2004-2009 Synopsys, Inc. Copyright 2010-2011 Mentor Graphics Corporation Copyright 2010-2011 Cadence Design Systems, Inc. All Rights Reserved Worldwide
Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
TITLE
Explicit Register Predictor
The uvm_reg_predictor class defines a predictor component, which is used to update the register model's mirror values based on transactions explicitly observed on a physical bus.