[source]

Module ibex_icache

Block Diagram of ibex_icache

Ports
Name	Type	Direction	Description
clk_i	wire logic	input	Clock and reset
rst_ni	wire logic	input
req_i	wire logic	input	Signal that the core would like instructions
branch_i	wire logic	input	Set the cache's address counter
addr_i	wire logic [31 : 0]	input
ready_i	wire logic	input	IF stage interface Pass fetched instructions to the core
valid_o	var logic	output
rdata_o	var logic [31 : 0]	output
addr_o	var logic [31 : 0]	output
err_o	var logic	output
err_plus2_o	var logic	output
instr_req_o	var logic	output	Instruction memory / interconnect interface Fetch instruction data from memory
instr_gnt_i	wire logic	input
instr_addr_o	var logic [31 : 0]	output
instr_rdata_i	wire logic [BUS_SIZE - 1 : 0]	input
instr_err_i	wire logic	input
instr_rvalid_i	wire logic	input
ic_tag_req_o	var logic [IC_NUM_WAYS - 1 : 0]	output	RAM IO
ic_tag_write_o	var logic	output
ic_tag_addr_o	var logic [IC_INDEX_W - 1 : 0]	output
ic_tag_wdata_o	var logic [TagSizeECC - 1 : 0]	output
ic_tag_rdata_i	wire logic [TagSizeECC - 1 : 0]	input
ic_data_req_o	var logic [IC_NUM_WAYS - 1 : 0]	output
ic_data_write_o	var logic	output
ic_data_addr_o	var logic [IC_INDEX_W - 1 : 0]	output
ic_data_wdata_o	var logic [LineSizeECC - 1 : 0]	output
ic_data_rdata_i	wire logic [LineSizeECC - 1 : 0]	input
ic_scr_key_valid_i	wire logic	input
ic_scr_key_req_o	var logic	output
icache_enable_i	wire logic	input	Cache status
icache_inval_i	wire logic	input
busy_o	var logic	output
ecc_error_o	var logic	output

Assertions
Name	Kind	Description
ibex_icache.size_param_legal	immediate assert	////////////// Assertions // ////////////// (IC_LINE_SIZE > 32)
ibex_icache.ecc_tag_param_legal	immediate assert	ECC primitives will need to be changed for different sizes (IC_TAG_SIZE <= 27)
ibex_icache.ecc_data_param_legal	immediate assert	(! ICacheECC \|\| (BUS_SIZE == 32))
ibex_icache.TagHitKnown	concurent assert	Lookups in the tag ram should always give a known result disable iff((!rst_ni)!=='0)! $isunknown((lookup_valid_ic1 & tag_hit_ic1))
ibex_icache.TagInvalidKnown	concurent assert	disable iff((!rst_ni)!=='0)! $isunknown((lookup_valid_ic1 & tag_invalid_ic1))

Always Blocks

always_comb @(): //////////////////////// Fill buffer tracking // ////////////////////////

always_comb @(): Mux the relevant beat of line data, based on the output address

always_comb @(): Mux the data from BUS_SIZE to halfword This muxing realigns data when instruction words are split across BUS_W e.g. word 1 |----|h1| word 0 |h0|----| --> |h1|h0| 31 15 0 31 15 0

always_comb @(): Invalidation (writing all entries in the tag RAM with an invalid tag) occurs straight out of reset and after any invalidation request (signalled via icache_inval_i). An invalidation request coming whilst another is writing tags causes the invalidation to start again. This ensures a new scramble key is requested where a previous one is in use. TODO: Ditch this behaviour for non-secure ibex?

FSM Transitions for inval_state_q
#	Current State	Next State	Condition
1	OUT_OF_RESET	AWAIT_SCRAMBLE_KEY	[EMPTY]
2	AWAIT_SCRAMBLE_KEY	INVAL_CACHE	[(ic_scr_key_valid_i)]
3	INVAL_CACHE	AWAIT_SCRAMBLE_KEY	[(icache_inval_i)]
4	INVAL_CACHE	IDLE	[(!(icache_inval_i) && (& inval_index_q))]
5	IDLE	AWAIT_SCRAMBLE_KEY	[(icache_inval_i)]