[source]

Module prim_generic_and2

Widthin0_i[Width-1:0]logicin1_i[Width-1:0]logicout_ologic[Width-1:0]

Block Diagram of prim_generic_and2

Parameters

Name

Default

Description

Width

1

Ports

Name

Type

Direction

Description

in0_i

wire logic [Width - 1 : 0]

input

in1_i

wire logic [Width - 1 : 0]

input

out_o

var logic [Width - 1 : 0]

output