[source]

Module ibex_core

PMPEnablePMPGranularityPMPNumRegionsPMPRstCfgPMPRstAddrPMPRstMsecCfgMHPMCounterNumMHPMCounterWidthRV32ERV32MRV32BBranchTargetALUWritebackStageICacheICacheECCBusSizeECCTagSizeECCLineSizeECCBranchPredictorDbgTriggerEnDbgHwBreakNumResetAllRndCnstLfsrSeedRndCnstLfsrPermSecureIbexDummyInstructionsRegFileECCRegFileDataWidthMemECCMemDataWidthDmBaseAddrDmAddrMaskDmHaltAddrDmExceptionAddrclk_ilogicrst_nilogichart_id_i[31:0]logicboot_addr_i[31:0]logicinstr_gnt_ilogicinstr_rvalid_ilogicinstr_rdata_i[MemDataWidth-1:0]logicinstr_err_ilogicdata_gnt_ilogicdata_rvalid_ilogicdata_rdata_i[MemDataWidth-1:0]logicdata_err_ilogicrf_rdata_a_ecc_i[RegFileDataWidth-1:0]logicrf_rdata_b_ecc_i[RegFileDataWidth-1:0]logicic_tag_rdata_i[TagSizeECC-1:0]logicic_data_rdata_i[LineSizeECC-1:0]logicic_scr_key_valid_ilogicirq_software_ilogicirq_timer_ilogicirq_external_ilogicirq_fast_i[14:0]logicirq_nm_ilogicdebug_req_ilogicfetch_enable_iibex_mubi_tinstr_req_ologicinstr_addr_ologic[31:0]data_req_ologicdata_we_ologicdata_be_ologic[3:0]data_addr_ologic[31:0]data_wdata_ologic[MemDataWidth-1:0]dummy_instr_id_ologicdummy_instr_wb_ologicrf_raddr_a_ologic[4:0]rf_raddr_b_ologic[4:0]rf_waddr_wb_ologic[4:0]rf_we_wb_ologicrf_wdata_wb_ecc_ologic[RegFileDataWidth-1:0]ic_tag_req_ologic[IC_NUM_WAYS-1:0]ic_tag_write_ologicic_tag_addr_ologic[IC_INDEX_W-1:0]ic_tag_wdata_ologic[TagSizeECC-1:0]ic_data_req_ologic[IC_NUM_WAYS-1:0]ic_data_write_ologicic_data_addr_ologic[IC_INDEX_W-1:0]ic_data_wdata_ologic[LineSizeECC-1:0]ic_scr_key_req_ologicirq_pending_ologiccrash_dump_ocrash_dump_tdouble_fault_seen_ologicrvfi_validlogicrvfi_orderlogic[63:0]rvfi_insnlogic[31:0]rvfi_traplogicrvfi_haltlogicrvfi_intrlogicrvfi_modelogic[1:0]rvfi_ixllogic[1:0]rvfi_rs1_addrlogic[4:0]rvfi_rs2_addrlogic[4:0]rvfi_rs3_addrlogic[4:0]rvfi_rs1_rdatalogic[31:0]rvfi_rs2_rdatalogic[31:0]rvfi_rs3_rdatalogic[31:0]rvfi_rd_addrlogic[4:0]rvfi_rd_wdatalogic[31:0]rvfi_pc_rdatalogic[31:0]rvfi_pc_wdatalogic[31:0]rvfi_mem_addrlogic[31:0]rvfi_mem_rmasklogic[3:0]rvfi_mem_wmasklogic[3:0]rvfi_mem_rdatalogic[31:0]rvfi_mem_wdatalogic[31:0]rvfi_ext_pre_miplogic[31:0]rvfi_ext_post_miplogic[31:0]rvfi_ext_nmilogicrvfi_ext_nmi_intlogicrvfi_ext_debug_reqlogicrvfi_ext_debug_modelogicrvfi_ext_rf_wr_suppresslogicrvfi_ext_mcyclelogic[63:0]rvfi_ext_mhpmcounterslogic[31:0]rvfi_ext_mhpmcountershlogic[31:0]rvfi_ext_ic_scr_key_validlogicrvfi_ext_irq_validlogicalert_minor_ologicalert_major_internal_ologicalert_major_bus_ologiccore_busy_oibex_mubi_t

Block Diagram of ibex_core

Top level module of the ibex RISC-V core

Parameters

Name

Default

Description
PMPEnable

1'b0
PMPGranularity

0
PMPNumRegions

4
PMPRstCfg

ibex_pkg::PmpCfgRst
PMPRstAddr

ibex_pkg::PmpAddrRst
PMPRstMsecCfg

ibex_pkg::PmpMseccfgRst
MHPMCounterNum

0
MHPMCounterWidth

40
RV32E

1'b0
RV32M

RV32MFast
RV32B

RV32BNone
BranchTargetALU

1'b0
WritebackStage

1'b0
ICache

1'b0
ICacheECC

1'b0
BusSizeECC

BUS_SIZE
TagSizeECC

IC_TAG_SIZE
LineSizeECC

IC_LINE_SIZE
BranchPredictor

1'b0
DbgTriggerEn

1'b0
DbgHwBreakNum

1
ResetAll

1'b0
RndCnstLfsrSeed

RndCnstLfsrSeedDefault
RndCnstLfsrPerm

RndCnstLfsrPermDefault
SecureIbex

1'b0
DummyInstructions

1'b0
RegFileECC

1'b0
RegFileDataWidth

32
MemECC

1'b0
MemDataWidth

MemECC?32+7:32
DmBaseAddr

32'h1A110000
DmAddrMask

32'h00000FFF
DmHaltAddr

32'h1A110800
DmExceptionAddr

32'h1A110808
Ports

Name

Type

Direction

Description
clk_i

wire logic

input

Clock and Reset
rst_ni

wire logic

input

verilator lint_off IMPERFECTSCH

hart_id_i

wire logic [31 : 0]

input

verilator lint_on IMPERFECTSCH

boot_addr_i

wire logic [31 : 0]

input
instr_req_o

var logic

output

Instruction memory interface
instr_gnt_i

wire logic

input
instr_rvalid_i

wire logic

input
instr_addr_o

var logic [31 : 0]

output
instr_rdata_i

wire logic [MemDataWidth - 1 : 0]

input
instr_err_i

wire logic

input
data_req_o

var logic

output

Data memory interface
data_gnt_i

wire logic

input
data_rvalid_i

wire logic

input
data_we_o

var logic

output
data_be_o

var logic [3 : 0]

output
data_addr_o

var logic [31 : 0]

output
data_wdata_o

var logic [MemDataWidth - 1 : 0]

output
data_rdata_i

wire logic [MemDataWidth - 1 : 0]

input
data_err_i

wire logic

input
dummy_instr_id_o

var logic

output

Register file interface
dummy_instr_wb_o

var logic

output
rf_raddr_a_o

var logic [4 : 0]

output
rf_raddr_b_o

var logic [4 : 0]

output
rf_waddr_wb_o

var logic [4 : 0]

output
rf_we_wb_o

var logic

output
rf_wdata_wb_ecc_o

var logic [RegFileDataWidth - 1 : 0]

output
rf_rdata_a_ecc_i

wire logic [RegFileDataWidth - 1 : 0]

input
rf_rdata_b_ecc_i

wire logic [RegFileDataWidth - 1 : 0]

input
ic_tag_req_o

var logic [IC_NUM_WAYS - 1 : 0]

output

RAMs interface
ic_tag_write_o

var logic

output
ic_tag_addr_o

var logic [IC_INDEX_W - 1 : 0]

output
ic_tag_wdata_o

var logic [TagSizeECC - 1 : 0]

output
ic_tag_rdata_i

wire logic [TagSizeECC - 1 : 0]

input
ic_data_req_o

var logic [IC_NUM_WAYS - 1 : 0]

output
ic_data_write_o

var logic

output
ic_data_addr_o

var logic [IC_INDEX_W - 1 : 0]

output
ic_data_wdata_o

var logic [LineSizeECC - 1 : 0]

output
ic_data_rdata_i

wire logic [LineSizeECC - 1 : 0]

input
ic_scr_key_valid_i

wire logic

input
ic_scr_key_req_o

var logic

output
irq_software_i

wire logic

input

Interrupt inputs
irq_timer_i

wire logic

input
irq_external_i

wire logic

input
irq_fast_i

wire logic [14 : 0]

input
irq_nm_i

wire logic

input

non-maskeable interrupt
irq_pending_o

var logic

output
debug_req_i

wire logic

input

Debug Interface
crash_dump_o

var crash_dump_t

output
double_fault_seen_o

var logic

output

SEC_CM

EXCEPTION.CTRL_FLOW.LOCAL_ESC

SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC
rvfi_valid

var logic

output
rvfi_order

var logic [63 : 0]

output
rvfi_insn

var logic [31 : 0]

output
rvfi_trap

var logic

output
rvfi_halt

var logic

output
rvfi_intr

var logic

output
rvfi_mode

var logic [1 : 0]

output
rvfi_ixl

var logic [1 : 0]

output
rvfi_rs1_addr

var logic [4 : 0]

output
rvfi_rs2_addr

var logic [4 : 0]

output
rvfi_rs3_addr

var logic [4 : 0]

output
rvfi_rs1_rdata

var logic [31 : 0]

output
rvfi_rs2_rdata

var logic [31 : 0]

output
rvfi_rs3_rdata

var logic [31 : 0]

output
rvfi_rd_addr

var logic [4 : 0]

output
rvfi_rd_wdata

var logic [31 : 0]

output
rvfi_pc_rdata

var logic [31 : 0]

output
rvfi_pc_wdata

var logic [31 : 0]

output
rvfi_mem_addr

var logic [31 : 0]

output
rvfi_mem_rmask

var logic [3 : 0]

output
rvfi_mem_wmask

var logic [3 : 0]

output
rvfi_mem_rdata

var logic [31 : 0]

output
rvfi_mem_wdata

var logic [31 : 0]

output
rvfi_ext_pre_mip

var logic [31 : 0]

output
rvfi_ext_post_mip

var logic [31 : 0]

output
rvfi_ext_nmi

var logic

output
rvfi_ext_nmi_int

var logic

output
rvfi_ext_debug_req

var logic

output
rvfi_ext_debug_mode

var logic

output
rvfi_ext_rf_wr_suppress

var logic

output
rvfi_ext_mcycle

var logic [63 : 0]

output
rvfi_ext_mhpmcounters

var logic [31 : 0]

output
rvfi_ext_mhpmcountersh

var logic [31 : 0]

output
rvfi_ext_ic_scr_key_valid

var logic

output
rvfi_ext_irq_valid

var logic

output
fetch_enable_i

wire ibex_mubi_t

input

CPU Control Signals SEC_CM: FETCH.CTRL.LC_GATED
alert_minor_o

var logic

output
alert_major_internal_o

var logic

output
alert_major_bus_o

var logic

output
core_busy_o

var ibex_mubi_t

output
Assertions

Name

Kind

Description

ibex_core.IbexMuBiSecureOnBottomBitSet

immediate assert

Multi-bit fetch enable used when SecureIbex == 1. When SecureIbex == 0 only use the bottom-bit of fetch_enable_i. Ensure the multi-bit encoding has the bottom bit set for on and unset for off so IbexMuBiOn/IbexMuBiOff can be used without needing to know the value of SecureIbex.

(IbexMuBiOn[0] == 1'b1)

ibex_core.IbexMuBiSecureOffBottomBitClear

immediate assert

 
(IbexMuBiOff[0] == 1'b0)

ibex_core.NoMemRFWriteWithoutPendingLoad

concurent assert

When writing back the result of a load, the load must have made it to writeback

disable iff((!rst_ni)!=='0)(rf_we_lsu |-> outstanding_load_wb)

ibex_core.NoMemRFWriteWithoutPendingLoad

concurent assert

 
disable iff((!rst_ni)!=='0)(rf_we_lsu |-> outstanding_load_id)

ibex_core.NoMemResponseWithoutPendingAccess

concurent assert

 
disable iff((!rst_ni)!=='0)(data_rvalid_i |-> (outstanding_load_resp | outstanding_store_resp))

ibex_core.NoExecWhenFetchEnableNotOn

concurent assert

When fetch is disabled, no instructions should be executed. Once fetch is disabled either the ID/EX stage is not valid or the PC of the ID/EX stage must remain as it was at disable. The ID/EX valid should not ressert once it has been cleared.

disable iff((!rst_ni)!=='0)(! fetch_enable_raw |=> ((~ instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~ $rose(instr_valid_id)))

ibex_core.IbexCsrOpValid

concurent assert

These assertions are in top-level as instr_valid_id required as the enable term

disable iff((!rst_ni)!=='0)(instr_valid_id |-> (csr_op inside {CSR_OP_READ, CSR_OP_WRITE, CSR_OP_SET, CSR_OP_CLEAR}))

ibex_core.IbexCsrWdataIntKnownKnownEnable

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(csr_op_en)

ibex_core.IbexCsrWdataIntKnown

concurent assert

 
disable iff((!rst_ni)!=='0)(csr_op_en |-> ! $isunknown(cs_registers_i.csr_wdata_int))

ibex_core.IllegalParamSecure

immediate assert

Certain parameter combinations are not supported

! (SecureIbex && (RV32M == RV32MNone))

ibex_core.MultDivFSMIdleOnIdReady

concurent assert

If the ID stage signals its ready the mult/div FSMs must be idle in the following cycle

disable iff((!rst_ni)!=='0)(id_in_ready |=> ex_block_i.sva_multdiv_fsm_idle)

Always Blocks

always_ff @(posedge clk_i or negedge rst_ni)

Pass the captured irq/debug_req/nmi state to the rvfi_ext interface tracking pipeline.

To correctly capture we need to factor in various enable terms, should there be a fault in this logic we won't tell the DV environment about a trap that should have been taken. So if there's no valid capture we grab the raw values of the irq/debug_req/nmi inputs whatever they are and the DV environment will see if a trap should have been taken but wasn't.

always_comb @()

Memory address/write data available first cycle of ld/st instruction from register read

always_comb @()

Capture read data from LSU when it becomes valid

always_comb @()

Byte enable based on data type

always_comb @()

Source registers 1 and 2 are read in the first instruction cycle Source register 3 is read in the second instruction cycle.

always_ff @(posedge clk_i or negedge rst_ni)

RD write register is refreshed only once per cycle and then it is kept stable for the cycle.

Instances

Submodules

  • ibex_core

    • cs_registers_i : ibex_cs_registers

    • ex_block_i : ibex_ex_block

    • g_core_busy_non_secure : [if !(SecureIbex)]

    • g_instr_req_gated_non_secure : [if !(SecureIbex)]

    • g_no_check_mem_response : [if !(SecureIbex)]

    • g_no_fcov_rf_ecc_err_a_id : [if !(RegFileECC)]

    • g_no_fcov_rf_ecc_err_b_id : [if !(RegFileECC)]

    • g_no_pmp : [if !(PMPEnable)]

    • g_rvfi_irq_valid : [for (genvar i=0;i<RVFI_STAGES+1;i=i+1)]

    • g_rvfi_no_rf_wr_suppress_wb : [if !(WritebackStage)]

    • g_rvfi_stages : [for (genvar i=0;i<RVFI_STAGES;i=i+1)]

    • gen_no_regfile_ecc : [if !(RegFileECC)]

    • gen_no_wb_stage : [if !(WritebackStage)]

    • gen_rvfi_no_wb_stage : [if !(WritebackStage)]

    • id_stage_i : ibex_id_stage

    • if_stage_i : ibex_if_stage

    • load_store_unit_i : ibex_load_store_unit

    • wb_stage_i : ibex_wb_stage

cs_registers_i (ibex_cs_registers) ex_block_i (ibex_ex_block) id_stage_i (ibex_id_stage) if_stage_i (ibex_if_stage) load_store_unit_i (ibex_load_store_unit) wb_stage_i (ibex_wb_stage) g_rvfi_irq_valid_first_stage g_rvfi_irq_valid_other_stages g_rvfi_irq_valid g_rvfi_stages u_ibex_core (ibex_core)

Flow Diagram of ibex_core

cs_registers_i (ibex_cs_registers) clk_i rst_ni hart_id_i priv_mode_id_o csr_mstatus_tw_o csr_mtvec_o csr_mtvec_init_i boot_addr_i csr_access_i csr_addr_i csr_op_i csr_op_en_i csr_rdata_o irq_software_i irq_timer_i irq_external_i irq_fast_i nmi_mode_i irq_pending_o irqs_o csr_mstatus_mie_o csr_mepc_o debug_mode_i debug_mode_entering_i debug_cause_i debug_csr_save_i csr_depc_o debug_single_step_o debug_ebreakm_o debug_ebreaku_o trigger_match_o pc_if_i pc_id_i pc_wb_i data_ind_timing_o dummy_instr_en_o dummy_instr_mask_o dummy_instr_seed_en_o dummy_instr_seed_o icache_enable_o ic_scr_key_valid_i csr_save_if_i csr_save_id_i csr_save_wb_i csr_restore_mret_i csr_restore_dret_i csr_save_cause_i csr_mcause_i csr_mtval_i illegal_csr_insn_o double_fault_seen_o instr_ret_i instr_ret_compressed_i instr_ret_spec_i instr_ret_compressed_spec_i jump_i branch_i branch_taken_i mem_load_i mem_store_i dside_wait_i mul_wait_i div_wait_i ex_block_i (ibex_ex_block) clk_i rst_ni alu_operator_i alu_operand_a_i alu_operand_b_i alu_instr_first_cycle_i bt_a_operand_i bt_b_operand_i multdiv_operator_i mult_en_i div_en_i mult_sel_i div_sel_i multdiv_signed_mode_i multdiv_operand_a_i multdiv_operand_b_i multdiv_ready_id_i data_ind_timing_i imd_val_we_o imd_val_d_o imd_val_q_i alu_adder_result_ex_o result_ex_o branch_target_o branch_decision_o ex_valid_o id_stage_i (ibex_id_stage) clk_i rst_ni instr_valid_i instr_rdata_i instr_rdata_alu_i instr_rdata_c_i instr_is_compressed_i instr_bp_taken_i instr_first_cycle_id_o instr_valid_clear_o id_in_ready_o icache_inval_o branch_decision_i pc_set_o pc_mux_o nt_branch_mispredict_o nt_branch_addr_o exc_pc_mux_o exc_cause_o illegal_c_insn_i instr_fetch_err_i instr_fetch_err_plus2_i pc_id_i ex_valid_i lsu_resp_valid_i alu_operator_ex_o alu_operand_a_ex_o alu_operand_b_ex_o imd_val_we_ex_i imd_val_d_ex_i imd_val_q_ex_o bt_a_operand_o bt_b_operand_o mult_en_ex_o div_en_ex_o mult_sel_ex_o div_sel_ex_o multdiv_operator_ex_o multdiv_signed_mode_ex_o multdiv_operand_a_ex_o multdiv_operand_b_ex_o multdiv_ready_id_o csr_access_o csr_op_o csr_addr_o csr_op_en_o csr_save_if_o csr_save_id_o csr_save_wb_o csr_restore_mret_id_o csr_restore_dret_id_o csr_save_cause_o csr_mtval_o priv_mode_i csr_mstatus_tw_i illegal_csr_insn_i data_ind_timing_i lsu_req_o lsu_we_o lsu_type_o lsu_sign_ext_o lsu_wdata_o lsu_req_done_i lsu_addr_incr_req_i lsu_addr_last_i csr_mstatus_mie_i irq_pending_i irqs_i irq_nm_i nmi_mode_o lsu_load_resp_intg_err_i lsu_store_resp_intg_err_i debug_mode_o debug_mode_entering_o debug_cause_o debug_csr_save_o debug_req_i debug_single_step_i debug_ebreakm_i debug_ebreaku_i trigger_match_i result_ex_i csr_rdata_i rf_waddr_id_o rf_wdata_id_o rf_we_id_o rf_waddr_wb_i rf_wdata_fwd_wb_i rf_write_wb_i en_wb_o instr_type_wb_o instr_perf_count_id_o ready_wb_i outstanding_load_wb_i outstanding_store_wb_i perf_jump_o perf_branch_o perf_tbranch_o perf_dside_wait_o perf_mul_wait_o perf_div_wait_o if_stage_i (ibex_if_stage) clk_i rst_ni boot_addr_i instr_req_o instr_addr_o instr_gnt_i instr_rvalid_i instr_rdata_i instr_bus_err_i ic_tag_req_o ic_tag_write_o ic_tag_addr_o ic_tag_wdata_o ic_tag_rdata_i ic_data_req_o ic_data_write_o ic_data_addr_o ic_data_wdata_o ic_data_rdata_i ic_scr_key_valid_i ic_scr_key_req_o instr_valid_id_o instr_rdata_id_o instr_rdata_alu_id_o instr_rdata_c_id_o instr_is_compressed_id_o instr_bp_taken_o instr_fetch_err_o instr_fetch_err_plus2_o illegal_c_insn_id_o dummy_instr_id_o pc_if_o pc_id_o pmp_err_if_i pmp_err_if_plus2_i instr_valid_clear_i pc_set_i pc_mux_i nt_branch_mispredict_i nt_branch_addr_i exc_pc_mux_i exc_cause dummy_instr_en_i dummy_instr_mask_i dummy_instr_seed_en_i dummy_instr_seed_i icache_enable_i icache_inval_i branch_target_ex_i csr_mepc_i csr_depc_i csr_mtvec_i csr_mtvec_init_o id_in_ready_i load_store_unit_i (ibex_load_store_unit) clk_i rst_ni data_gnt_i data_rvalid_i data_bus_err_i data_pmp_err_i data_addr_o data_we_o data_be_o data_wdata_o data_rdata_i lsu_we_i lsu_type_i lsu_wdata_i lsu_sign_ext_i lsu_rdata_o lsu_req_i adder_result_ex_i addr_incr_req_o addr_last_o lsu_req_done_o lsu_resp_valid_o load_resp_intg_err_o store_resp_intg_err_o perf_load_o perf_store_o wb_stage_i (ibex_wb_stage) clk_i rst_ni en_wb_i instr_type_wb_i pc_id_i instr_is_compressed_id_i instr_perf_count_id_i ready_wb_o rf_write_wb_o outstanding_load_wb_o outstanding_store_wb_o pc_wb_o perf_instr_ret_wb_o perf_instr_ret_compressed_wb_o perf_instr_ret_wb_spec_o perf_instr_ret_compressed_wb_spec_o rf_waddr_id_i rf_wdata_id_i rf_we_id_i dummy_instr_id_i rf_wdata_lsu_i rf_wdata_fwd_wb_o rf_waddr_wb_o lsu_resp_valid_i g_core_busy_non_secure g_instr_req_gated_non_secure g_no_check_mem_response g_no_fcov_rf_ecc_err_a_id g_no_fcov_rf_ecc_err_b_id g_no_pmp g_rvfi_irq_valid_first_stage g_rvfi_irq_valid_other_stages g_rvfi_irq_valid g_rvfi_no_rf_wr_suppress_wb g_rvfi_stages gen_no_regfile_ecc gen_no_wb_stage gen_rvfi_no_wb_stage u_ibex_core (ibex_core) clk_i rst_ni hart_id_i boot_addr_i instr_req_o instr_gnt_i instr_rvalid_i instr_addr_o instr_rdata_i instr_err_i data_gnt_i data_rvalid_i data_we_o data_be_o data_addr_o data_wdata_o data_rdata_i data_err_i ic_tag_req_o ic_tag_write_o ic_tag_addr_o ic_tag_wdata_o ic_tag_rdata_i ic_data_req_o ic_data_write_o ic_data_addr_o ic_data_wdata_o ic_data_rdata_i ic_scr_key_valid_i ic_scr_key_req_o irq_software_i irq_timer_i irq_external_i irq_fast_i irq_nm_i irq_pending_o debug_req_i double_fault_seen_o

Sub-Instances Diagram of ibex_core

cs_registers_i (ibex_cs_registers) clk_i rst_ni hart_id_i priv_mode_id_o priv_mode_lsu_o csr_mstatus_tw_o csr_mtvec_o csr_mtvec_init_i boot_addr_i csr_access_i csr_addr_i csr_wdata_i csr_op_i csr_op_en_i csr_rdata_o irq_software_i irq_timer_i irq_external_i irq_fast_i nmi_mode_i irq_pending_o irqs_o csr_mstatus_mie_o csr_mepc_o csr_mtval_o csr_pmp_cfg_o csr_pmp_addr_o csr_pmp_mseccfg_o debug_mode_i debug_mode_entering_i debug_cause_i debug_csr_save_i csr_depc_o debug_single_step_o debug_ebreakm_o debug_ebreaku_o trigger_match_o pc_if_i pc_id_i pc_wb_i data_ind_timing_o dummy_instr_en_o dummy_instr_mask_o dummy_instr_seed_en_o dummy_instr_seed_o icache_enable_o csr_shadow_err_o ic_scr_key_valid_i csr_save_if_i csr_save_id_i csr_save_wb_i csr_restore_mret_i csr_restore_dret_i csr_save_cause_i csr_mcause_i csr_mtval_i illegal_csr_insn_o double_fault_seen_o instr_ret_i instr_ret_compressed_i instr_ret_spec_i instr_ret_compressed_spec_i iside_wait_i jump_i branch_i branch_taken_i mem_load_i mem_store_i dside_wait_i mul_wait_i div_wait_i ex_block_i (ibex_ex_block) clk_i rst_ni alu_operator_i alu_operand_a_i alu_operand_b_i alu_instr_first_cycle_i bt_a_operand_i bt_b_operand_i multdiv_operator_i mult_en_i div_en_i mult_sel_i div_sel_i multdiv_signed_mode_i multdiv_operand_a_i multdiv_operand_b_i multdiv_ready_id_i data_ind_timing_i imd_val_we_o imd_val_d_o imd_val_q_i alu_adder_result_ex_o result_ex_o branch_target_o branch_decision_o ex_valid_o id_stage_i (ibex_id_stage) clk_i rst_ni ctrl_busy_o illegal_insn_o instr_valid_i instr_rdata_i instr_rdata_alu_i instr_rdata_c_i instr_is_compressed_i instr_bp_taken_i instr_req_o instr_first_cycle_id_o instr_valid_clear_o id_in_ready_o instr_exec_i icache_inval_o branch_decision_i pc_set_o pc_mux_o nt_branch_mispredict_o nt_branch_addr_o exc_pc_mux_o exc_cause_o illegal_c_insn_i instr_fetch_err_i instr_fetch_err_plus2_i pc_id_i ex_valid_i lsu_resp_valid_i alu_operator_ex_o alu_operand_a_ex_o alu_operand_b_ex_o imd_val_we_ex_i imd_val_d_ex_i imd_val_q_ex_o bt_a_operand_o bt_b_operand_o mult_en_ex_o div_en_ex_o mult_sel_ex_o div_sel_ex_o multdiv_operator_ex_o multdiv_signed_mode_ex_o multdiv_operand_a_ex_o multdiv_operand_b_ex_o multdiv_ready_id_o csr_access_o csr_op_o csr_addr_o csr_op_en_o csr_save_if_o csr_save_id_o csr_save_wb_o csr_restore_mret_id_o csr_restore_dret_id_o csr_save_cause_o csr_mtval_o priv_mode_i csr_mstatus_tw_i illegal_csr_insn_i data_ind_timing_i lsu_req_o lsu_we_o lsu_type_o lsu_sign_ext_o lsu_wdata_o lsu_req_done_i lsu_addr_incr_req_i lsu_addr_last_i csr_mstatus_mie_i irq_pending_i irqs_i irq_nm_i nmi_mode_o lsu_load_err_i lsu_load_resp_intg_err_i lsu_store_err_i lsu_store_resp_intg_err_i expecting_load_resp_o expecting_store_resp_o debug_mode_o debug_mode_entering_o debug_cause_o debug_csr_save_o debug_req_i debug_single_step_i debug_ebreakm_i debug_ebreaku_i trigger_match_i result_ex_i csr_rdata_i rf_raddr_a_o rf_rdata_a_i rf_raddr_b_o rf_rdata_b_i rf_ren_a_o rf_ren_b_o rf_waddr_id_o rf_wdata_id_o rf_we_id_o rf_rd_a_wb_match_o rf_rd_b_wb_match_o rf_waddr_wb_i rf_wdata_fwd_wb_i rf_write_wb_i en_wb_o instr_type_wb_o instr_perf_count_id_o ready_wb_i outstanding_load_wb_i outstanding_store_wb_i perf_jump_o perf_branch_o perf_tbranch_o perf_dside_wait_o perf_mul_wait_o perf_div_wait_o instr_id_done_o if_stage_i (ibex_if_stage) clk_i rst_ni boot_addr_i req_i instr_req_o instr_addr_o instr_gnt_i instr_rvalid_i instr_rdata_i instr_bus_err_i instr_intg_err_o ic_tag_req_o ic_tag_write_o ic_tag_addr_o ic_tag_wdata_o ic_tag_rdata_i ic_data_req_o ic_data_write_o ic_data_addr_o ic_data_wdata_o ic_data_rdata_i ic_scr_key_valid_i ic_scr_key_req_o instr_valid_id_o instr_new_id_o instr_rdata_id_o instr_rdata_alu_id_o instr_rdata_c_id_o instr_is_compressed_id_o instr_bp_taken_o instr_fetch_err_o instr_fetch_err_plus2_o illegal_c_insn_id_o dummy_instr_id_o pc_if_o pc_id_o pmp_err_if_i pmp_err_if_plus2_i instr_valid_clear_i pc_set_i pc_mux_i nt_branch_mispredict_i nt_branch_addr_i exc_pc_mux_i exc_cause dummy_instr_en_i dummy_instr_mask_i dummy_instr_seed_en_i dummy_instr_seed_i icache_enable_i icache_inval_i icache_ecc_error_o branch_target_ex_i csr_mepc_i csr_depc_i csr_mtvec_i csr_mtvec_init_o id_in_ready_i pc_mismatch_alert_o if_busy_o load_store_unit_i (ibex_load_store_unit) clk_i rst_ni data_req_o data_gnt_i data_rvalid_i data_bus_err_i data_pmp_err_i data_addr_o data_we_o data_be_o data_wdata_o data_rdata_i lsu_we_i lsu_type_i lsu_wdata_i lsu_sign_ext_i lsu_rdata_o lsu_rdata_valid_o lsu_req_i adder_result_ex_i addr_incr_req_o addr_last_o lsu_req_done_o lsu_resp_valid_o load_err_o load_resp_intg_err_o store_err_o store_resp_intg_err_o busy_o perf_load_o perf_store_o wb_stage_i (ibex_wb_stage) clk_i rst_ni en_wb_i instr_type_wb_i pc_id_i instr_is_compressed_id_i instr_perf_count_id_i ready_wb_o rf_write_wb_o outstanding_load_wb_o outstanding_store_wb_o pc_wb_o perf_instr_ret_wb_o perf_instr_ret_compressed_wb_o perf_instr_ret_wb_spec_o perf_instr_ret_compressed_wb_spec_o rf_waddr_id_i rf_wdata_id_i rf_we_id_i dummy_instr_id_i rf_wdata_lsu_i rf_we_lsu_i rf_wdata_fwd_wb_o rf_waddr_wb_o rf_wdata_wb_o rf_we_wb_o dummy_instr_wb_o lsu_resp_valid_i lsu_resp_err_i instr_done_wb_o perf_iside_wait id_in_ready instr_valid_id unused_illegal_insn_id illegal_insn_id data_req_o data_req_out pmp_req_err lsu_resp_err lsu_load_err lsu_store_err dummy_instr_id_o dummy_instr_id dummy_instr_wb_o dummy_instr_wb rf_raddr_a_o rf_raddr_a rf_waddr_wb_o rf_waddr_wb rf_we_wb_o rf_we_wb rf_raddr_b_o rf_raddr_b crash_dump_o.current_pc pc_id crash_dump_o.next_pc pc_if crash_dump_o.last_data_addr lsu_addr_last crash_dump_o.exception_pc csr_mepc crash_dump_o.exception_addr crash_dump_mtval alert_minor_o icache_ecc_error alert_major_internal_o rf_ecc_err_comb pc_mismatch_alert csr_shadow_err alert_major_bus_o lsu_load_resp_intg_err lsu_store_resp_intg_err instr_intg_err outstanding_load_id outstanding_store_id fetch_enable_raw fetch_enable_i csr_wdata alu_operand_a_ex rvfi_valid rvfi_stage_valid rvfi_order rvfi_stage_order rvfi_insn rvfi_stage_insn rvfi_trap rvfi_stage_trap rvfi_halt rvfi_stage_halt rvfi_intr rvfi_stage_intr rvfi_mode rvfi_stage_mode rvfi_ixl rvfi_stage_ixl rvfi_rs1_addr rvfi_stage_rs1_addr rvfi_rs2_addr rvfi_stage_rs2_addr rvfi_rs3_addr rvfi_stage_rs3_addr rvfi_rs1_rdata rvfi_stage_rs1_rdata rvfi_rs2_rdata rvfi_stage_rs2_rdata rvfi_rs3_rdata rvfi_stage_rs3_rdata rvfi_rd_addr rvfi_stage_rd_addr rvfi_rd_wdata rvfi_stage_rd_wdata rvfi_pc_rdata rvfi_stage_pc_rdata rvfi_pc_wdata rvfi_stage_pc_wdata rvfi_mem_addr rvfi_stage_mem_addr rvfi_mem_rmask rvfi_stage_mem_rmask rvfi_mem_wmask rvfi_stage_mem_wmask rvfi_mem_rdata rvfi_stage_mem_rdata rvfi_mem_wdata rvfi_stage_mem_wdata rvfi_rd_addr_wb rf_waddr_wb rvfi_rd_wdata_wb rf_wdata_wb rf_we_wb rf_wdata_lsu rvfi_rd_we_wb rf_we_wb rf_we_lsu rvfi_ext_nmi rvfi_ext_stage_nmi rvfi_ext_nmi_int rvfi_ext_stage_nmi_int rvfi_ext_debug_req rvfi_ext_stage_debug_req rvfi_ext_debug_mode rvfi_ext_stage_debug_mode rvfi_ext_mcycle rvfi_ext_stage_mcycle rvfi_ext_mhpmcounters rvfi_ext_stage_mhpmcounters rvfi_ext_mhpmcountersh rvfi_ext_stage_mhpmcountersh rvfi_ext_ic_scr_key_valid rvfi_ext_stage_ic_scr_key_valid rvfi_ext_irq_valid rvfi_ext_stage_irq_valid rvfi_id_done instr_id_done rvfi_stage_order_d rvfi_stage_order dummy_instr_id new_debug_req debug_req_i debug_mode new_nmi irq_nm_i nmi_mode debug_mode new_nmi_int nmi_mode debug_mode new_irq irq_pending_o csr_mstatus_mie priv_mode_id nmi_mode debug_mode rvfi_intr_d rvfi_set_trap_pc_q instr_first_cycle_id rvfi_intr_q unused_fcov_rf_ecc_err_a_id fcov_rf_ecc_err_a_id unused_fcov_rf_ecc_err_b_id fcov_rf_ecc_err_b_id fcov_csr_read_only csr_op csr_access csr_op_en illegal_insn_id unused_fcov_csr_read_only fcov_csr_read_only fcov_csr_write csr_access csr_op_en illegal_insn_id unused_fcov_csr_write fcov_csr_write rvfi_ext_pre_mip rvfi_ext_stage_pre_mip.irq_software rvfi_ext_stage_pre_mip.irq_timer rvfi_ext_stage_pre_mip.irq_external rvfi_ext_stage_pre_mip.irq_fast rvfi_ext_post_mip rvfi_ext_stage_post_mip.irq_software rvfi_ext_stage_post_mip.irq_timer rvfi_ext_stage_post_mip.irq_external rvfi_ext_stage_post_mip.irq_fast rvfi_mem_addr_d alu_adder_result_ex instr_first_cycle_id rvfi_mem_addr_q rvfi_mem_wdata_d lsu_wdata rvfi_mem_wdata_q rvfi_mem_rdata_d rf_wdata_lsu lsu_resp_valid rvfi_mem_rdata_q rvfi_mem_mask_int lsu_type rvfi_insn_id instr_rdata_c_id instr_is_compressed_id instr_rdata_id rvfi_rs3_data_d instr_first_cycle_id multdiv_operand_a_ex rvfi_rs3_addr_d rf_raddr_a rvfi_rs1_data_d rvfi_rs1_data_q rf_ren_a rvfi_rs1_addr_d rvfi_rs1_addr_q rvfi_rs2_data_d rvfi_rs2_data_q multdiv_operand_b_ex rf_ren_b rvfi_rs2_addr_d rvfi_rs2_addr_q rf_raddr_b rvfi_rd_addr_d rvfi_rd_addr_wb rvfi_rd_we_wb rvfi_instr_new_wb rvfi_rd_addr_q rvfi_rd_wdata_d rvfi_rd_wdata_q rvfi_rd_wdata_wb rvfi_set_trap_pc_d rvfi_set_trap_pc_q pc_set pc_mux_id exc_pc_mux_id rvfi_id_done pc_at_fetch_disable rst_ni clk_i pc_id fetch_enable_i last_fetch_enable last_fetch_enable captured_valid rst_ni clk_i instr_valid_id new_debug_req new_irq new_nmi new_nmi_int captured_valid captured_debug_req captured_nmi captured_mip captured_nmi irq_nm_i captured_nmi_int captured_debug_req debug_req_i rvfi_irq_valid ready_wb rvfi_ext_stage_pre_mip rst_ni clk_i rvfi_irq_valid instr_valid_id captured_valid captured_mip rvfi_ext_stage_nmi irq_nm_i captured_nmi rvfi_ext_stage_nmi_int captured_nmi_int rvfi_ext_stage_debug_req debug_req_i captured_debug_req rvfi_mem_addr_q rst_ni clk_i rvfi_mem_addr_d rvfi_mem_rdata_q rvfi_mem_rdata_d rvfi_mem_wdata_q rvfi_mem_wdata_d rvfi_rs1_data_q rst_ni clk_i rvfi_rs1_data_d rvfi_rs1_addr_q rvfi_rs1_addr_d rvfi_rs2_data_q rvfi_rs2_data_d rvfi_rs2_addr_q rvfi_rs2_addr_d rvfi_rd_addr_q rst_ni clk_i rvfi_rd_addr_d rvfi_rd_wdata_q rvfi_rd_wdata_d rvfi_set_trap_pc_q rst_ni clk_i rvfi_set_trap_pc_d rvfi_intr_q rvfi_intr_d core_busy_o ctrl_busy if_busy lsu_busy g_core_busy_non_secure unused_fetch_enable fetch_enable_i instr_req_gated instr_req_int fetch_enable_i instr_exec fetch_enable_i g_instr_req_gated_non_secure lsu_load_err lsu_load_err_raw lsu_store_err lsu_store_err_raw rf_we_lsu lsu_rdata_valid unused_expecting_load_resp_id expecting_load_resp_id unused_expecting_store_resp_id expecting_store_resp_id g_no_check_mem_response fcov_rf_ecc_err_a_id g_no_fcov_rf_ecc_err_a_id fcov_rf_ecc_err_b_id g_no_fcov_rf_ecc_err_b_id unused_priv_lvl_ls priv_mode_lsu unused_csr_pmp_addr csr_pmp_addr unused_csr_pmp_cfg csr_pmp_cfg unused_csr_pmp_mseccfg csr_pmp_mseccfg pmp_req_err pmp_req_err pmp_req_err g_no_pmp rvfi_ext_stage_irq_valid rst_ni clk_i rvfi_irq_valid g_rvfi_irq_valid_first_stage rvfi_ext_stage_irq_valid rst_ni clk_i rvfi_ext_stage_irq_valid g_rvfi_irq_valid_other_stages g_rvfi_irq_valid rvfi_ext_rf_wr_suppress g_rvfi_no_rf_wr_suppress_wb rvfi_stage_halt rst_ni clk_i rvfi_id_done rvfi_stage_halt rvfi_wb_done rvfi_stage_trap rvfi_trap_id rvfi_stage_trap rvfi_trap_wb rvfi_stage_intr rvfi_intr_d rvfi_stage_intr rvfi_stage_order rvfi_stage_order_d rvfi_stage_order rvfi_stage_insn rvfi_insn_id rvfi_stage_insn rvfi_stage_mode priv_mode_id rvfi_stage_mode rvfi_stage_ixl rvfi_stage_ixl rvfi_stage_rs1_addr rvfi_rs1_addr_d rvfi_stage_rs1_addr rvfi_stage_rs2_addr rvfi_rs2_addr_d rvfi_stage_rs2_addr rvfi_stage_rs3_addr rvfi_rs3_addr_d rvfi_stage_rs3_addr rvfi_stage_pc_rdata pc_id rvfi_stage_pc_rdata rvfi_stage_pc_wdata rvfi_stage_pc_wdata branch_target_ex pc_set pc_if rvfi_stage_mem_rmask rvfi_mem_mask_int rvfi_stage_mem_rmask rvfi_stage_mem_wmask rvfi_stage_mem_wmask data_we_o rvfi_stage_valid rvfi_stage_valid_d rvfi_stage_rs1_rdata rvfi_rs1_data_d rvfi_stage_rs1_rdata rvfi_stage_rs2_rdata rvfi_rs2_data_d rvfi_stage_rs2_rdata rvfi_stage_rs3_rdata rvfi_rs3_data_d rvfi_stage_rs3_rdata rvfi_stage_rd_wdata rvfi_rd_wdata_d rvfi_stage_rd_addr rvfi_rd_addr_d rvfi_stage_mem_rdata rvfi_mem_rdata_d rvfi_stage_mem_wdata rvfi_mem_wdata_d rvfi_stage_mem_wdata rvfi_stage_mem_addr rvfi_mem_addr_d rvfi_stage_mem_addr rvfi_ext_stage_pre_mip rvfi_ext_stage_pre_mip rvfi_ext_stage_irq_valid rvfi_ext_stage_post_mip rvfi_ext_stage_post_mip rvfi_ext_stage_nmi rvfi_ext_stage_nmi rvfi_ext_stage_nmi_int rvfi_ext_stage_nmi_int rvfi_ext_stage_debug_req rvfi_ext_stage_debug_req rvfi_ext_stage_debug_mode debug_mode rvfi_ext_stage_debug_mode rvfi_ext_stage_mcycle rvfi_ext_stage_mcycle rvfi_ext_stage_mhpmcounters rvfi_ext_stage_mhpmcounters rvfi_ext_stage_mhpmcountersh rvfi_ext_stage_mhpmcountersh rvfi_ext_stage_ic_scr_key_valid rvfi_ext_stage_ic_scr_key_valid g_rvfi_stages unused_rf_ren_a rf_ren_a unused_rf_ren_b rf_ren_b unused_rf_rd_a_wb_match rf_rd_a_wb_match unused_rf_rd_b_wb_match rf_rd_b_wb_match rf_wdata_wb_ecc_o rf_wdata_wb rf_rdata_a rf_rdata_a_ecc_i rf_rdata_b rf_rdata_b_ecc_i rf_ecc_err_comb gen_no_regfile_ecc outstanding_load_resp outstanding_load_id outstanding_store_resp outstanding_store_id gen_no_wb_stage rvfi_stage_valid_d rvfi_id_done dummy_instr_id rvfi_instr_new_wb instr_new_id rvfi_trap_id rvfi_trap_wb rvfi_wb_done instr_done_wb gen_rvfi_no_wb_stage u_ibex_core (ibex_core) clk_i rst_ni hart_id_i boot_addr_i instr_req_o instr_gnt_i instr_rvalid_i instr_addr_o instr_rdata_i instr_err_i data_req_o data_gnt_i data_rvalid_i data_we_o data_be_o data_addr_o data_wdata_o data_rdata_i data_err_i dummy_instr_id_o dummy_instr_wb_o rf_raddr_a_o rf_raddr_b_o rf_waddr_wb_o rf_we_wb_o rf_wdata_wb_ecc_o rf_rdata_a_ecc_i rf_rdata_b_ecc_i ic_tag_req_o ic_tag_write_o ic_tag_addr_o ic_tag_wdata_o ic_tag_rdata_i ic_data_req_o ic_data_write_o ic_data_addr_o ic_data_wdata_o ic_data_rdata_i ic_scr_key_valid_i ic_scr_key_req_o irq_software_i irq_timer_i irq_external_i irq_fast_i irq_nm_i irq_pending_o debug_req_i crash_dump_o double_fault_seen_o rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr rvfi_mode rvfi_ixl rvfi_rs1_addr rvfi_rs2_addr rvfi_rs3_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rs3_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata rvfi_ext_pre_mip rvfi_ext_post_mip rvfi_ext_nmi rvfi_ext_nmi_int rvfi_ext_debug_req rvfi_ext_debug_mode rvfi_ext_rf_wr_suppress rvfi_ext_mcycle rvfi_ext_mhpmcounters rvfi_ext_mhpmcountersh rvfi_ext_ic_scr_key_valid rvfi_ext_irq_valid fetch_enable_i alert_minor_o alert_major_internal_o alert_major_bus_o core_busy_o

Schematic Diagram of ibex_core