[source]

Entity cache_replacement_policy

REPLACEMENT_POLICYCACHE_WAYSClockstd_logicResetstd_logicReplacestd_logicTagAccessstd_logicReadWritestd_logicInvalidatestd_logicHitWay[log2ceilnz ( CACHE_WAYS ) - 1 downto 0]std_logic_vectorReplaceWaystd_logic_vector[log2ceilnz ( CACHE_WAYS ) - 1 downto 0]

Block Diagram of cache_replacement_policy

Supported policies:

Abbr.

Policies

supported

RR

round robin

not yet

RAND

random

not yet

CLOCK

clock algorithm

not yet

LRU

least recently used

YES

LFU

least frequently used

not yet

Command thruth table:

TagAccess

ReadWrite

Invalidate

Replace

Command

0

0

None

1

0

0

0

TagHit and reading a cache line

1

1

0

0

TagHit and writing a cache line

1

0

1

0

TagHit and invalidate a cache line (while reading)

1

1

1

0

TagHit and invalidate a cache line (while writing)

0

0

1

Replace cache line

In a set-associative cache, each cache-set has its own instance of this component.

The input HitWay specifies the accessed way in a fully-associative or set-associative cache.

The output ReplaceWay identifies the way which will be replaced as next by a replace command. In a set-associative cache, this is the way in a specific cache set (see above).

Generics

Name

Type

Default

Description

REPLACEMENT_POLICY

string

"LRU"

CACHE_WAYS

positive

32

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Replace

std_logic

in

replacement interface

ReplaceWay

std_logic_vector

out

TagAccess

std_logic

in

cacheline usage update interface

ReadWrite

std_logic

in

Invalidate

std_logic

in

HitWay

std_logic_vector

in