Component ddrio_in_altera

Block Diagram of ddrio_in_altera

Vendor specific modules ----------------------------------------------

Generics

Name	Type	Initial Value	Description
BITS	positive
INIT_VALUE	bit_vector	x"FFFFFFFF"

Ports

Name	Direction	Type	Description
Clock	in	std_logic
ClockEnable	in	std_logic
DataIn_high	out	std_logic_vector
DataIn_low	out	std_logic_vector
Pad	in	std_logic_vector

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