Entity uart_rx

Block Diagram of uart_rx

UART Receiver: 1 Start + 8 Data + 1 Stop

Generics

Name	Type	Default	Description
SYNC_DEPTH	natural	2	use zero for already clock-synchronous rx

Ports

Name	Type	Direction	Description
clk	std_logic	in	Global Control
rst	std_logic	in
bclk_x8	std_logic	in	Bit Clock and RX Line bit clock, eight strobes per bit length
rx	std_logic	in
do	std_logic_vector	out	Byte Stream Output
stb	std_logic	out

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