Entity ocram_sp

Block Diagram of ocram_sp

Inferring / instantiating single port memory, with:

• single clock, clock enable,

• 1 read/write port.

Command Truth Table:

ce	we	Command
0	X	No operation
1	0	Read from memory
1	1	Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

When writing data, the read output will output the new data (in the following clock cycle) which is aka. "write-first behavior". This behavior also applies to Altera M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" (UG-01068) is wrong.

Generics

Name	Type	Default	Description
A_BITS	positive		number of address bits
D_BITS	positive		number of data bits
FILENAME	string	""	file-name for RAM initialization

Ports

Name	Type	Direction	Description
clk	std_logic	in	clock
ce	std_logic	in	clock enable
we	std_logic	in	write enable
a	unsigned	in	address
d	std_logic_vector	in	write data
q	std_logic_vector	out	read output

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