[source]

Component arith_trng

BITSclkstd_logicrndstd_logic_vector[BITS - 1 downto 0]

Block Diagram of arith_trng

Generics

Name

Type

Initial Value

Description

BITS

positive

Width: Number of Oscillators

Ports

Name

Direction

Type

Description

clk

in

std_logic

Clock

rnd

out

std_logic_vector

Random Oscillator Samples