[source]

Entity arith_sqrt

Nrststd_logicclkstd_logicarg[N - 1 downto 0]std_logic_vectorstartstd_logicsqrtstd_logic_vector[( N - 1 ) / 2 downto 0]rdystd_logic

Block Diagram of arith_sqrt

Iterative Square Root Extractor.

Its computation requires (N+1)/2 steps for an argument bit width of N.

Generics

Name

Type

Default

Description

N

positive

:= 8 -- Bit Width of Argument

Ports

Name

Type

Direction

Description

rst

std_logic

in

Global Control Reset (synchronous)

clk

std_logic

in

Clock

arg

std_logic_vector

in

Inputs Radicand

start

std_logic

in

Start Strobe

sqrt

std_logic_vector

out

Outputs Result

rdy

std_logic

out

Ready / Done