Component fifo_cc_got_tempgot

Block Diagram of fifo_cc_got_tempgot

Generics

Name	Type	Initial Value	Description
D_BITS	positive		Data Width
MIN_DEPTH	positive		Minimum FIFO Depth
DATA_REG	boolean	false	Store Data Content in Registers
STATE_REG	boolean	false	Registered Full/Empty Indicators
OUTPUT_REG	boolean	false	Registered FIFO Output
ESTATE_WR_BITS	natural	0	Empty State Bits
FSTATE_RD_BITS	natural	0	Full State Bits

Ports

Name	Direction	Type	Description
rst	in	std_logic	Global Reset and Clock
clk	in	std_logic
put	in	std_logic	Writing Interface Write Request
din	in	std_logic_vector	Input Data
full	out	std_logic
estate_wr	out	std_logic_vector
got	in	std_logic	Reading Interface Read Completed
dout	out	std_logic_vector	Output Data
valid	out	std_logic
fstate_rd	out	std_logic_vector
commit	in	std_logic
rollback	in	std_logic

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